1. Field of the Invention
The present invention relates to a display device. In particular, the present invention relates to a display device in which a pixel circuit is formed three-dimensionally with the use of a field-effect transistor where a semiconductor layer is provided on an insulating surface.
2. Description of the Related Art
In recent years, a structure using a semiconductor substrate which is referred to as silicon on insulator (hereinafter also referred to as “SOI”) in which a thin single crystal semiconductor layer is provided on an insulating surface has been attracting attention. In this structure, an active region (a channel formation region) of a field-effect transistor (FET, also simply referred to as a transistor), which has been formed of bulk single crystal silicon, is formed of a single crystal silicon thin film.
As a method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (e.g., see Patent Document 1: Japanese Published Patent Application No. 2000-124092). The hydrogen ion implantation separation method is a method in which hydrogen ions are implanted into a silicon wafer to form a microbubble layer at a certain depth from the surface, and a thin silicon layer is bonded to another silicon wafer with the microbubble layer as a cleavage plane. In addition to heat treatment for separation of the silicon layer, it is necessary to perform heat treatment in an oxidizing atmosphere to form an oxide film on the silicon layer, remove the oxide film, and perform heat treatment at a temperature of 1000° C. to 1300° C. to increase bonding strength. Therefore, it is difficult to bond a silicon layer with desired bonding strength to a substrate like a glass substrate which cannot resist high temperature treatment, and there is a technical obstacle in simply applying the hydrogen ion implantation separation method to a field-effect transistor which forms a pixel of a display device.
On the other hand, a display device provided with a transistor which forms a pixel with the use of a technique of stacking thin film circuits three-dimensionally by provision of a thin film circuit including a transistor which is formed using a separation technique and a transfer technique and a connection electrode for connecting an external circuit to the thin film circuit is disclosed (see Patent Document 2: Japanese Published Patent Application No. 2004-349513).